Description

26LS32 Receiver features four independent receiver chains which comply with EIA Standards for the Electrical Characteristics of Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs are, three–state structures which are forced to a high impedance state when Pin 4 is a Logic “0” and Pin 12 is a Logic “1.” A PNP device buffers each output control pin to assure minimum loading for either Logic “1” or logic “0” inputs.